Recently, the evolution of embedded systems has shown a strong trend towards application-specific, single-chip solutions. As a result, application-specific instruction set processors (ASIP) are more and more replacing off-the-shelf processors in such systems-on-chip (SoC). One of the key factors for a successful design of application-specific instruction set processors (ASIP) is an efficient architecture exploration phase. The objective of the architecture exploration is to reduce the huge design space in order to find the best-suited architecture for a given application under a number of constraints, such as performance, power consumption, chip size, and flexibility. Although there are a number of analytical approaches, large parts of the design space exploration still have to be carried out by simulating alternative architecture implementations with simulation models. It becomes obvious that the design methodology and simulation performance have a significant impact on the efficiency of the exploration process, hence, on the quality of the architecture implementation and the design time. Moreover, the design of the processor core (including the instruction set) and peripherals have very different simulation requirements.
FIG. 1 depicts a conventional simulation environment used to simulate an architecture (or platform) that in this case includes multiple processor cores and hardware, such that the platform may be debugged. The hardware debugger 150 executes a simulation kernel 160 comprising a hardware simulation model 180 and two processor core simulation models (CPU1 and CPU2 simulations 175). The hardware debugger 150 has an application program interface (API) to communicate with the hardware simulation model 180. However, in order for the hardware debugger 150 to communicate with the processor core simulation models 175, which is needed to perform the overall simulation, the processor core simulations 175 each have a software wrapper 185. Processor core debuggers 170 are used to control and observe the processor core simulations 175, such that the processor cores may be debugged.
Hardware developers typically need cycle accurate simulation models and are willing to accept a slower simulation to get to full cycle accuracy. A cycle-accurate simulation model is one in which the state of the simulation model at the end of each clock cycle accurately reflects the state a real-world processor or hardware being modeled would have. Software developers on the other hand are much less dependent on complete cycle accuracy of the simulation model. Software developers desire very high simulation speeds and are typically willing to trade simulation accuracy for speed. However, even if the simulation model is not cycle accurate, it still needs to correctly model the software. That is, even if the state of the simulation model does not necessarily reflect the state that the real-world processor or hardware would have at the end of each clock cycle, the overall behavior of the simulation model must still match the real-world processor or hardware being modeled. Thus, the simulation should be behaviorally accurate. Furthermore, some software developers (e.g. device driver developers) need full cycle accuracy in only some parts of the simulation model.
Conventionally, hardware developers and software developers use different simulation models because of the aforementioned different simulation requirements. Typically, a set of simulation models are used to simulate a computer platform. For example, the set may comprise a processor core simulation, an instruction set simulation, a memory simulation model, a bus simulation model, and simulation models for various peripherals (e.g., hardware simulations). Time and effort is spent developing separate sets of simulation models for the hardware and the software developers. Further, the two sets of simulation models must be validated as being functionally equivalent. Also, it is difficult to achieve a fast simulation that has behaviorally correct simulation results. Typically, substantial manual work is required to obtain to high simulation speed while still obtaining behaviorally correct simulation results